搜索资源列表
635022219123437500
- 基于FPGA的CAM设计，CAM设计的方案和代码。-Using Block RAM for High Performance Read/Write CAMs
arm_fpga.tar
- 实现TQ2440与FPGA的通信功能，将FPGA当作ARM的一个外设，通信方式为静态RAM方式。在代码中，我实现了向FPGA读写数据的功能，已经做过测试。没问题-make the TQ2440 board commuciate with the FPGA board.
epcs35f
- 该程序实现了在ALTERA FPGA上搭建NIOS系统，实现程序在EPCS4上保存，在内部RAM 上运行-The program to build on in the ALTERA FPGA NIOS system, program EPCS4 saved on the internal RAM to run
16bit_ram
- 利用vhdl语言在fpga实现十六位的ram 使用非常方便-Using vhdl fpga implementation sixteen languages in the ram is very convenient to use
ramipcore
- 使用vhdl 语言在fpga环境下实现ram ip core-Environment in fpga vhdl language used to achieve ram ip core
90166ram_16bit
- 基于FPGA的片没ram的读写功能代码，能够写入和读出16bit的数据，适合初学者学习和模仿使用-FPGA-based tablets did not ram read and write function code can be written and read out the 16bit data, suitable for beginners to learn and imitate Use
33017ram(1)
- 基于FPGA的片没ram的读写功能代码，能够写入和读出16bit的数据，适合初学者学习和模仿使用-FPGA-based tablets did not ram read and write function code can be written and read out the 16bit data, suitable for beginners to learn and imitate Use
cos_value
- 用于生成FPGA中RAM所需要的初始化文件dds.mif,此文件生成的是余弦波形。-This document of .m can generate document of .mif to provide data for RAM of FPGA.
emifa_ram
- FPGA与DSP的EMIF通信，EMIF的RAM这方面相应的程序-FPGA and DSP EMIF communication
ramIPcore
- 基于quartusII的ram调用，利用FPGA自身的blockram创立ram的ip core-Based on the ram quartusII calls itself blockram created using FPGA ram' s ip core
fpgawritetoram
- fpga向RAM中写数据，数据宽度32位，利用VHDL编写。-FPGA write data to ram in 32bit data bus,write in VHDL.
Latch_sram
- FPGA内部集成RAM和锁存器模块设计，欢迎大家来验证-FPGA internal RAM and latches integrated module design, welcome to verify
IPRAM
- FPGA内置RAM,调用tools里面的IP核，生成一个双口的RAM，用来存储数据。然后可以用SignalTAP II查看波形或者数据。-FPGA built-in RAM, which is called IP core tools to generate a dual port RAM, used to store data. You can then view the waveform or use SignalTAP II data.
9288Test3
- AD9288 100MhzAD转换芯片的控制代码，用Verilog语言实现。采集数据存储于FPGA内置RAM中。-Conversion chip AD9288 100MhzAD control code, using Verilog language. FPGA collected data is stored in the built-in RAM.
generate-mif-file
- 如何生成mif文件 用于导入fpga的RAM存储中-How to generate mif file for importing RAM memory in fpga
SDRAMping-pong-memory-structure
- 双口RAM 的乒乓存储结构（芯片型号CY7C09279） 应用场合为FPGA向双口RAM不断写入数据，PCI总线从RAM读取数据。[已调试验证]-Dual-port RAM, ping-pong memory structure (chip model CY7C09279) applications for the FPGA to the dual-port RAM write data continuously, PCI bus read data from RAM. [Debugging
ROM
- vhdl中的ROM程序，包括matlab表格程序，调用FPGA里的RAM实现ROM功能-The ROM vhdl procedures, including matlab spreadsheet program, call the FPGA to achieve ROM functions in the RAM
top
- 调用FPGA中的IP核的RAM的顶层文件-Call the FPGA IP core RAM top-level file
ddr3_uniphy_siv_example_restored
- A system that is written in Verilog to be able to read and write data to a DDR3 RAM by Altera FPGA
ram_test
- NIOS实现RAM-test,新做好一块带SRAM的FPGA板子，学习NIOS，必定可以用到的测试SRAM的代码。-NIOS achieve RAM-test, a new well with SRAM FPGA board, the learning NIOS, must be used to test SRAM code.